– Led SoC/RTL verification (SystemVerilog/UVM) for complex SoC designs integrating custom AI accelerators and
secure data paths.
– Developed optimized FPGA/SoC designs using Verilog, HLS (C/C++), and Vivado HLS for embedded AI applications,
focusing on PPA (Power, Performance, Area) trade-offs.
– Designed radiation-tolerant FPGA-based DSP systems for satellite communication, including signal processing accelerators
for on-board AI-based image compression and packetization.
– Developed imaging satellite payloads and high-speed multi-layer PCBs, implemented FPGA-based DSP/RF processing,
and conducted Signal/Power Integrity analysis for high-frequency reliability. Awarded with: Distinguished
Performance Award for PakTes-1A satellite launch.
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