-Control components such as ADC, DAC, PLL, … via EMIF, SPI interfaces. -Design DDC, including utilizing DDS and applying decimation CIC, FIR filters (IP core). -Demodulate and channelize wrapped signal into appropriate VDE, ASM, and AIS channels. -Languages and tools: VerilogHDL, Vivado, ISE, TI CCS

-Control EMIF and McBSP interfaces for FPGA and DSP communication. -Design transmitter and receiver to do digital modulation and demodulation, including designing filters. -Verify by investigating eye pattern and modulation constellation. -Languages and tools: MATLAB/Simulink, VerilogHDL, Vivado.

-Control EMIF and McASP interfaces for FPGA and DSP communication. -Design transmitter and receiver to do digital modulation and demodulation. -Implement cross correlation algorithm for waveform pattern recognition. -Languages and tools: MATLAB/Simulink, VerilogHDL, Vivado, TI CCS.

-Design PCB schematic for communication board using USB hub for upstream connection to main board, downstream connection to LAN (through USB-to-Ethernet IC) and compass (through USB-to-UART IC). -Tool: OrCAD, PADS.

-Propose new high-performance architecture for implementing the orthogonal matching pursuit algorithm for compressively sensed signal reconstruction -Propose novel pipelined systolic architecture and optimized scheduling strategy -Design new processing elements for systolic array, Distributed-Arithmetic-based and Sum-of-Product-based matrix multiplication architectures -Programming: VerilogHDL, Vivado, DC Compiler, VCS, ZedBoard XC7Z020CLG484-1