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Sense of responsibility, reliability and carefulness - Eager to study, full of ambition, strong desire to do things - Able to adapt to new surroundings, work well with others - Strong analytical skill
Carrière
Publications
Résumé de carrière par IA
Les informations sur la carrière de sont encore insuffisantes pour générer un résumé. Le résumé de carrière s'affichera une fois que plus d'informations auront été ajoutées.
- Gain knowledge and ability related to electronic devices, electric circuits and digital circuits to understand the components and the operating theory.
- Use MATLAB/Simulink System Generator for communication system modelling, simulation and verification.
- Build interface control modules, combine the whole project using Vivado (FSM, IP core).
- Interface and communicate DSP with FPGA via TI CCS.
- Design PCB schematic in OrCAD and layout in PADS.
- Experience with circuit design related tools (oscilloscope, spectrum analyzer, signal generator), and verification tools utilizing built-in design such as ChipScope, ILA IP core.
- Have in-depth knowledge of Xilinx FPGA series (Artix-7, Virtex-7, Kintex-7, Spartan-3, Zed board, Zybo board), and TI MCU OMAP, TMS C66xx.
Robert Bosch Engineering & Business Solutions Vietnam
2014년 7월 - 2016년 1월 · 1년 7개월
-Analyze customers’ requirements to make specification for hardware and software designs
-Integrate Basic Component and Functional Component to the entire module, fix bugs and deliver released software
-Use automotive testing tools (Cantata, SharkCC) and administrative tools (SDOM, RequestOne)
-Programming: C, Microsoft Visual Studio 2010
CENTIC, Information and Telecommunication Department of DaNang
2013년 10월 - 2014년 3월 · 6개월
-Obtain knowledge about RTOS and develop embedded application to control intersection traffic
-Work in project to design UART communication chip, going through every stages from Specification to Layout place & route
-Programming: VerilogHDL, DC Compiler, VCS, PrimeTime,…
-Final Project: UART Communication Chip Design
-Modules included
Digital Signal Processing
FPGA Implementation
-Graduation Project: Security System using Combination of Passcode Lock and Face Recognition
-GPA: 3.17/4.0
-Modules included
Digital Image Processing Algorithm
Fundamentals of Digital Signal Processing
MCU Programming
Voir plus
Activité
Activité récente
Récompense 2
Certification 3
Projet 7
프로젝트
VHF 모뎀 RF 송수신 증폭기 보드 보완제작 및 제어프로그램 제작
A&D System · 2018년 3월 - 현재 · 8년
-Control components such as ADC, DAC, PLL, … via EMIF, SPI interfaces.
-Design DDC, including utilizing DDS and applying decimation CIC, FIR filters (IP core).
-Demodulate and channelize wrapped signal into appropriate VDE, ASM, and AIS channels.
-Languages and tools: VerilogHDL, Vivado, ISE, TI CCS
프로젝트
해상 VHF 대역 디지털 통신용 송/수신 필터부 FPGA 구현 용역
A&D System · 2018년 3월 - 현재 · 8년
-Control EMIF and McBSP interfaces for FPGA and DSP communication.
-Design transmitter and receiver to do digital modulation and demodulation, including designing filters.
-Verify by investigating eye pattern and modulation constellation.
-Languages and tools: MATLAB/Simulink, VerilogHDL, Vivado.
프로젝트
수중 장거리 통신모뎀용 FPGA 구현 용역
A&D System · 2018년 3월 - 현재 · 8년
-Control EMIF and McASP interfaces for FPGA and DSP communication.
-Design transmitter and receiver to do digital modulation and demodulation.
-Implement cross correlation algorithm for waveform pattern recognition.
-Languages and tools: MATLAB/Simulink, VerilogHDL, Vivado, TI CCS.
프로젝트
휴대용 개발 R&D 사업
A&D System · 2018년 3월 - 현재 · 8년
-Design PCB schematic for communication board using USB hub for upstream connection to main board, downstream connection to LAN (through USB-to-Ethernet IC) and compass (through USB-to-UART IC).
-Tool: OrCAD, PADS.
프로젝트
Optical Modulation and Signal Processing for Realizing 400G Optical Transmission Technology
Myongji University, MPEES · 2016년 9월 - 2018년 1월 · 1년 5개월
-Propose new high-performance architecture for implementing the orthogonal matching pursuit algorithm for compressively sensed signal reconstruction
-Propose novel pipelined systolic architecture and optimized scheduling strategy
-Design new processing elements for systolic array, Distributed-Arithmetic-based and Sum-of-Product-based matrix multiplication architectures
-Programming: VerilogHDL, Vivado, DC Compiler, VCS, ZedBoard XC7Z020CLG484-1
Langues
베트남어
원어민
영어
고급 (자유로운 의사소통)
한국어
중급 (업무상 의사소통)
일본어
초급
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